Efficient Realization of Arithmetic Algorithms with Weighted Collections of Posibits and Negabits

The most common uses of negatively weighted bits (negabits), normally assuming the arithmetic value −1 (respectively 0) for logical 1 (0) state, are as the most significant bit of 2’s-complement numbers and as the negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalized digit sets and the practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells, such as half/full adders, bit compressors, and counters. These cells have been highly optimized for a host of simple and composite figures of merit involving delay, power, and area, and they are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2’s-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2 + 1) multiplier, where the partial products are represented in WBS with IEN. We show that by using standard reduction cells, the partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to the final sum. The thoroughly explained process of conversion to BSD is also new. Keywords––(4;2)-compressor, Digit set, Full-adder cell, Inverted encoding of negabits, Parallel compressor, Parallel counter, Redundant number representation, Signed-digit arithmetic, Weighted bit-set encoding, G. Jaberipur is also affiliated with School of Computer Science, Inst. for Research in Fundamental Science (IPM).